Memory reconfiguration for system-on-chip yield improvement
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Науковедение
Автор:
Vrezh Sargsyan
Год издания: 2014
Кол-во страниц: 8
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Интернет-журнал «НАУКОВЕДЕНИЕ» Выпуск 2, март – апрель 2014 Опубликовать статью в журнале - http://publ.naukovedenie.ru Институт Государственного управления, права и инновационных технологий (ИГУПИТ) Связаться с редакцией: publishing@naukovedenie.ru 1 http://naukovedenie.ru 170TAVN214 Vrezh Sargsyan National Research University «MIET» Russia, Zelenograd E-Mail: s.vrezh@gmail.com Memory reconfiguration for system-on-chip yield improvement Abstract: One of the most important issues in the design and manufacturing process of system on-chip is the difficulty of achieving a profitable chip yield. In modern system-on-chip embedded memories are the dominating components. System chips usually contain hundreds, and in some cases - thousands of different types of memory elements. And hence, overall chip yield becomes largely dependent on memory yield. Modern system-on-chips include dedicated built–in infrastructures intended for testing, diagnosis and repair of embedded memory devices. The advantages of using built– in infrastructures are the absence of any additional external equipment and relatively low cost, as well as the ability to test the device by user. Memory repair is performed by disabling memory defective elements (row / column) and enabling redundant elements based on repair signature. In this paper, memory array reconfiguration mechanism in described. Memory built-in self-test and repair infrastructure is designed, which significantly reduces the memory repair signature loading time. Keywords: System-on-chip; intellectual property; embedded test and repair; yield; embedded memory deuce; memory reconfiguration; integrated circuit; power domain, simulation and synthesis. Identification number of article 170TAVN214